3df6cc9de6
For GICD and GICR a SOC needs to implement 2 callbacks to get the base of those interrupt controllers. For all the cpu GIC the code loops over all the DEVICE_PATH_GICC_V3 devices in a similar fashion to how x86 lapics are added. It's up to the SOC to add those devices to the tree. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5074d0a76316e854b7801e14b3241f88e805b02f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76132 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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| .. | ||
| dram | ||
| azalia.h | ||
| azalia_device.h | ||
| cardbus.h | ||
| device.h | ||
| gpio.h | ||
| i2c.h | ||
| i2c_bus.h | ||
| i2c_simple.h | ||
| mdio.h | ||
| mmio.h | ||
| path.h | ||
| pci.h | ||
| pci_def.h | ||
| pci_ehci.h | ||
| pci_ids.h | ||
| pci_mmio_cfg.h | ||
| pci_ops.h | ||
| pci_rom.h | ||
| pci_type.h | ||
| pciexp.h | ||
| pcix.h | ||
| pnp.h | ||
| pnp_def.h | ||
| pnp_ops.h | ||
| pnp_type.h | ||
| resource.h | ||
| smbus.h | ||
| smbus_def.h | ||
| smbus_host.h | ||
| soundwire.h | ||
| spi.h | ||
| usbc_mux.h | ||
| xhci.h | ||