coreboot/src
Angel Pons 3dea2b63ee soc/intel/common/block/systemagent/memmap.c: Align cached region
When asked to place cbmem_top(), FSP does not seem to care about
alignment. It can return an address that is MTRR poison, which will
exhaust all variable MTRRs when trying to set up caching for CBMEM.
This will make memory-mapped flash and TSEG caching fail as well.

Safeguard against this by aligning the region to cache to half of its
size, and move it upwards to compensate. It is assumed that caching
memory above the provided bootloader TOLUM address is inconsequential.

TEST=Boot Purism Librem Mini WHL, observe no MTRR exhaustion error
     messages in console. The boot process also feels more fluid.

Change-Id: Ic64fd6d3d9e8ab4c78d68b910a476f9c4eb2d353
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-03 17:04:03 +00:00
..
acpi acpigen: Make acpigen_write_opregion() argument const 2020-10-21 22:24:27 +00:00
arch arch/x86/smbios: Populate SMBIOS type 7 with cache information 2020-10-26 06:54:04 +00:00
commonlib lib/libpayload: Replace strapping_ids with new board configuration entry 2020-10-30 15:25:28 +00:00
console console/init: Drop CONSOLE_LEVEL_CONST 2020-10-26 06:48:45 +00:00
cpu cpu/x86/mp_init: Add support for x86_64 2020-11-03 02:09:12 +00:00
device azalia: Treat all negative return values as errors 2020-11-02 10:41:15 +00:00
drivers soc/intel/common: Create common Intel FSP reset code block 2020-11-02 10:43:40 +00:00
ec ec/system76/ec: Add battery charging thresholds 2020-11-02 06:23:36 +00:00
include include/list.h: Add support for GCC9+ 2020-11-03 09:11:21 +00:00
lib lib/libpayload: Replace strapping_ids with new board configuration entry 2020-10-30 15:25:28 +00:00
mainboard mb/google/volteer/var/volteer2: Merge common_soc_config 2020-11-02 17:31:55 +00:00
northbridge {cpu,nb}/intel/haswell: Drop unnecessary UL suffix 2020-10-31 10:08:59 +00:00
security sec/intel/txt/Kconfig: Remove the menu for including ACMs 2020-10-28 12:55:43 +00:00
soc soc/intel/common/block/systemagent/memmap.c: Align cached region 2020-11-03 17:04:03 +00:00
southbridge azalia: Use HDA_GCTL_CRST macro as unset-mask 2020-11-02 10:41:35 +00:00
superio superio/nuvoton: Factor out equivalent Kconfig option 2020-10-19 07:06:20 +00:00
vendorcode vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425 2020-11-02 04:43:39 +00:00
Kconfig soc/intel/xeon_sp: Move function debug macros 2020-10-29 16:44:19 +00:00