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Robert Zieba 3db7b46804 soc/amd/cezanne: Update XHCI GPE to use constant 
The GPE number used for XHCI has now been defined in AMD's common code
in CB:67936. Change over existing code to use this new definition.

BRANCH=guybrush
BUG=b:186792595
TEST=Ran on nipperkin device and verified that XHCI events string use
GPE 31.

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I9c2a44f7d2eb47422ae8c585e5e01ea0b420d461
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69917
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09 19:40:38 +00:00
..
amd soc/amd/cezanne: Update XHCI GPE to use constant 2023-03-09 19:40:38 +00:00
cavium treewide: Remove duplicated include <device/pci.h> 2023-02-01 03:03:34 +00:00
example/min86 soc: Add SPDX license headers to Makefiles 2022-10-31 03:27:13 +00:00
intel soc/intel/broadwell/gma: don't unconditionally remap all GPU PCI IDs 2023-03-09 16:57:07 +00:00
mediatek mb/google/geralt: Add MAX98390 support for Geralt 2023-03-05 15:47:57 +00:00
nvidia treewide: stop calling custom TPM log "TCPA" 2023-01-11 16:00:55 +00:00
qualcomm Revert "soc/qualcomm: Increase SPI frequency to 75 MHz" 2023-02-24 19:28:24 +00:00
rockchip cbmem_top_chipset: Change the return value to uintptr_t 2022-11-18 16:00:45 +00:00
samsung treewide: Fix old-style declarations 2023-01-17 04:23:49 +00:00
sifive/fu540 cbmem_top_chipset: Change the return value to uintptr_t 2022-11-18 16:00:45 +00:00
ti src/soc/ti: Remove unnecessary space after casts 2022-11-22 13:42:28 +00:00
ucb/riscv cbmem_top_chipset: Change the return value to uintptr_t 2022-11-18 16:00:45 +00:00