Ronald G. Minnich 3d302b03f4 riscv: add a variable to control trap management ... This variable can be set in a debugger (e.g. Spike) to finely control which traps go to coreboot and which go to the supervisor. Change-Id: I292264c15f002c41cf8d278354d8f4c0efbd0895 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17404 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>		2016-11-14 01:09:12 +01:00
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arm	src/arch: Improve code formatting	2016-09-12 20:05:30 +02:00
arm64	arm64: Use 'payload' format for ATF instead of 'stage'	2016-10-06 21:49:52 +02:00
mips	build system: remove CBFSTOOL_PRE1_OPTS	2016-05-03 11:40:49 +02:00
power8	region: Add writeat and eraseat support	2016-06-24 20:48:12 +02:00
riscv	riscv: add a variable to control trap management	2016-11-14 01:09:12 +01:00
x86	ACPI S3: Remove HIGH_MEMORY_SAVE where possible	2016-11-09 20:52:07 +01:00