Change-Id: I3d14a40b4ed0dcc216dcac883e33749b7808f00d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
30 lines
1 KiB
C
30 lines
1 KiB
C
#ifndef DEVICE_PCIEXP_H
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#define DEVICE_PCIEXP_H
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/* (c) 2005 Linux Networx GPL see COPYING for details */
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enum aspm_type {
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PCIE_ASPM_NONE = 0,
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PCIE_ASPM_L0S = 1,
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PCIE_ASPM_L1 = 2,
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PCIE_ASPM_BOTH = 3,
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};
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#define ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET 16
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#define ASPM_LTR_L12_THRESHOLD_VALUE_MASK (0x3ff << ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET)
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#define ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET 29
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#define ASPM_LTR_L12_THRESHOLD_SCALE_MASK (0x7 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET)
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/* Latency tolerance reporting, max non-snoop latency value 3.14ms */
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#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US 0x1003
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/* Latency tolerance reporting, max snoop latency value 3.14ms */
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#define PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003
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void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
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unsigned int max_devfn);
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void pciexp_scan_bridge(struct device *dev);
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extern struct device_operations default_pciexp_ops_bus;
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unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap);
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#endif /* DEVICE_PCIEXP_H */
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