Kyösti Mälkki 3d00092a46 UPSTREAM: intel/cache_as_ram_ht.inc: Fix include ... Reference to CACHE_AS_RAM was from the days we had romcc boards using socket_mPGA605. Change-Id: If397db83a01adeda4dd18d8b4c6e89bf0984264a Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Original-Reviewed-on: https://review.coreboot.org/15224 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> (cherry-picked from commit 831a7ef541) Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/354185 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>		2016-06-20 20:09:57 -07:00
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allwinner	drivers/uart: Use uart_platform_refclk for all UART models	2016-05-09 18:45:44 +02:00
amd	UPSTREAM: Move definitions of HIGH_MEMORY_SAVE	2016-06-20 20:09:50 -07:00
armltd	vboot2: add verstage	2015-01-27 01:41:40 +01:00
dmp	x86 chipsets: Link non-code flow CHIPSET_BOOTBLOCK_INCLUDE files	2015-12-30 18:34:08 +01:00
intel	UPSTREAM: intel/cache_as_ram_ht.inc: Fix include	2016-06-20 20:09:57 -07:00
qemu-power8	cpu/qemu-power8: don't enable it for qemu-x86	2016-02-19 20:03:52 +01:00
qemu-x86	qemu-x86: Enable SMP support	2015-12-08 15:54:27 +01:00
ti	drivers/uart: Use uart_platform_refclk for all UART models	2016-05-09 18:45:44 +02:00
via	cpu/via/c7: Don't manually include udelay_io.c	2016-03-10 16:56:23 +01:00
x86	UPSTREAM: intel/sch: Merge northbridge and southbridge in src/soc	2016-05-20 17:08:20 -07:00
Kconfig	cpu: Add a way to use microcode .h files back to the build	2015-11-10 19:22:40 +01:00
Makefile.inc	cpu: Add a way to use microcode .h files back to the build	2015-11-10 19:22:40 +01:00