Shelley Chen 3cce7a0311 soc/intel/cannonlake: Add field to identify single channel memory ... Variants of Hatch need to accommodate single channel DDR. Also, removing const modifier as we'll need to set these fields incrementally now. For the single channel configuration, we set MemorySpdPtr10 to 0. For the dual channel configuration, we set MemorySpdPtr10 to MemorySpdPtr00. BUG=b:123062346, b:122959294 BRANCH=None TEST=Boot into current boards and ensure that we have 2 channels as expected Change-Id: Ice22b103664187834e255d1359bfd9b51993b5b6 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31262 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-02-21 11:31:19 +00:00
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apollolake	soc/intel: Add mem_rank info in SMBIOS	2019-02-18 20:25:42 +00:00
baytrail	soc/intel/baytrail: Don't use CAR_GLOBAL	2019-02-13 13:01:12 +00:00
braswell	src/soc/intel/braswell: Use DEVICE_NOOP	2019-01-20 21:02:43 +00:00
broadwell	soc/intel/broadwell: Don't use CAR_GLOBAL	2019-02-13 13:01:09 +00:00
cannonlake	soc/intel/cannonlake: Add field to identify single channel memory	2019-02-21 11:31:19 +00:00
common	soc/intel/common: Add whiskeylake celeron v-0 support	2019-02-19 22:00:40 +00:00
denverton_ns	soc/intel/denverton_ns: Add ACPI T-States and P-States	2019-01-28 13:33:30 +00:00
fsp_baytrail	Drop leftover debug function declarations	2019-01-23 09:26:25 +00:00
fsp_broadwell_de	src: Use macro ACPI_FADT_LEGACY_FREE	2019-02-15 16:24:02 +00:00
icelake	soc/intel: Add mem_rank info in SMBIOS	2019-02-18 20:25:42 +00:00
quark	mb/intel/galileo: Drop the FSP1.1 option	2019-02-11 12:28:52 +00:00
skylake	soc/intel: Add mem_rank info in SMBIOS	2019-02-18 20:25:42 +00:00
Kconfig	src/cpu: Remove dead sourced lines	2018-11-15 10:25:20 +00:00