John Zhao 3ba2c1a63e mb/google/volteer: Set FORCE_PWR low at boot time ... While FORCE_PWR is set high, it prevents retimer from entering low power state. S0ix failure occurs while USB4 Gatkex is connected on Port-0. This change sets FORCE_PWR(GPP_H10) low. This FORCE_PWR GPIO will be toggled by kernel through DSM method while updating retimer firmware. BUG=b:174166586 Cq-Depend: chromium:2594438 TEST=Verifed s0ix cycles with USB4 Gatkex connected on Port-0. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ie4b442e1078379c522a94bfdc00cd99e6f9b8170 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-01-11 07:36:52 +00:00
..
acpi	mb/x/acpi_tables: Rename to mainboard_fill_gnvs()	2021-01-10 11:29:10 +00:00
arch	arch/x86/Makefile.inc: Clean up generated assembly stubs	2021-01-08 08:10:04 +00:00
commonlib
console
cpu	mb/emulation/qemu: Copy page tables to DRAM in assembly	2021-01-11 07:34:19 +00:00
device	device: Add new Kconfig VGA_ROM_RUN_DEFAULT for mainboard user	2021-01-10 17:50:29 +00:00
drivers	ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocations	2021-01-10 11:15:10 +00:00
ec	ec/google/chromeec: add SSFC CBI support	2021-01-08 08:25:42 +00:00
include	soc/intel: Replace acpi_init_gnvs()	2021-01-10 11:39:28 +00:00
lib	arch/x86: Move prologue to .init section	2021-01-07 11:02:03 +00:00
mainboard	mb/google/volteer: Set FORCE_PWR low at boot time	2021-01-11 07:36:52 +00:00
northbridge	nb/intel/gm45: Guard macro parameters	2021-01-10 23:03:33 +00:00
security	*/Makefile.inc: Add some INTERMEDIATE targets to .PHONY	2021-01-08 08:08:07 +00:00
soc	soc/amd/picasso: Separate GPIO define into gpio_defs.h	2021-01-11 07:36:29 +00:00
southbridge	sb/intel/bd82x6x: Use PCH_LPC_DEV macro	2021-01-10 15:42:05 +00:00
superio
vendorcode	vc/intel/FSP2_0/CPX-SP: update to FSP ww01 release	2021-01-11 07:36:10 +00:00
Kconfig