Keith Hui 1ac19e28ee cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. ... Bring from coreboot v1 support for initializing L2 cache on Slot 1 Pentium II/III CPUs, code names Klamath, Deschutes and Katmai. Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with Pentium III 600MHz, Katmai core. Also add missing include of model_68x in slot_1, to address a similar problem fixed for model_6bx by r5945. Also change Deschutes CPU init sequence to match Katmai. Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: http://review.coreboot.org/122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>		2011-08-04 08:10:12 +02:00
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arch/x86	Add xhcbios and ahcibios rom handling	2011-07-22 20:02:22 +02:00
boot	more ifdef -> if fixes.	2011-04-21 21:26:58 +00:00
console	Do full flush on uart8250 only at end of printk.	2011-07-12 11:36:20 +02:00
cpu	cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.	2011-08-04 08:10:12 +02:00
devices	more ifdef -> if fixes	2011-04-21 20:45:45 +00:00
drivers	Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an	2011-04-26 23:47:04 +00:00
ec	T60: undock on external power loss	2011-06-23 14:12:26 +02:00
include	cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.	2011-08-04 08:10:12 +02:00
lib	Do full flush on uart8250 only at end of printk.	2011-07-12 11:36:20 +02:00
mainboard	Remove debugging code, or convert it to be selected by kconfig	2011-08-03 21:28:14 +02:00
northbridge	Update AMD SR5650 and SB700	2011-07-22 00:20:59 +02:00
pc80	X60: trigger save cmos on volume/brightness change	2011-06-15 08:51:18 +02:00
southbridge	Update AMD SR5650 and SB700	2011-07-22 00:20:59 +02:00
superio	Update AMD SR5650 and SB700	2011-07-22 00:20:59 +02:00
vendorcode	Update AMD SR5650 and SB700	2011-07-22 00:20:59 +02:00
Kconfig	added a config option for ACPI debugging	2011-07-02 00:49:53 +02:00
Kconfig.deprecated_options	some ifdef --> if fixes	2011-04-21 20:24:43 +00:00