coreboot/src
Duncan Laurie 3b70ad8ecf soc/intel/common: Use per-soc definition for BAR sizes
The various platform BARs are not always the same size across different
SOCs, so use the defined size rather than a hardcoded value.

This results in the following change on TGL which increased the MCHBAR
size to 128K:

-system 00:00: [mem 0xfedc0000-0xfeddffff] has been reserved
+system 00:00: [mem 0xfedc0000-0xfedc7fff] has been reserved

And fixes the following error output from the kernel:

resource sanity check: requesting [mem 0xfedc0000-0xfedcdfff],
  which spans more than pnp 00:00 [mem 0xfedc0000-0xfedc7fff]

Change-Id: I82796c2fc81dec883f3c69ae7bdcedc7d3f16c64
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-11-20 00:27:21 +00:00
..
acpi ACPI: Define acpi_get_preferred_pm_profile() 2020-11-19 22:58:41 +00:00
arch ACPI S3: Split arch-agnostic parts 2020-11-19 22:58:11 +00:00
commonlib commonlib: Add timestamp values for forced delays 2020-11-16 11:01:37 +00:00
console console: Override uart base address 2020-11-09 07:46:10 +00:00
cpu ACPI S3: Replace acpi_is_wakeup() 2020-11-19 14:48:31 +00:00
device device/pci: Add NULL check for PCI driver's .ops 2020-11-16 12:15:38 +00:00
drivers src/drivers/i2c/rx6110sa: Omit _HID temporarily 2020-11-19 15:04:33 +00:00
ec ec/google/chromeec: Add more wrappers for regulator control 2020-11-18 06:13:12 +00:00
include ACPI: Define acpi_get_preferred_pm_profile() 2020-11-19 22:58:41 +00:00
lib ACPI S3: Replace acpi_is_wakeup() 2020-11-19 14:48:31 +00:00
mainboard mb/google/volteer/variants: Set TCSS PCIe RP0 to hidden by default 2020-11-20 00:27:04 +00:00
northbridge nb/intel/sandybridge: Correct some whitespace issues 2020-11-19 23:04:20 +00:00
security vboot: stop implementing VbExDisplayScreen 2020-11-18 05:49:46 +00:00
soc soc/intel/common: Use per-soc definition for BAR sizes 2020-11-20 00:27:21 +00:00
southbridge soc/amd/common: remove SOC_AMD_COMMON_BLOCK Kconfig symbol 2020-11-18 16:08:17 +00:00
superio superio/smsc/sio1036: Support 16-bit IO port addressing 2020-11-18 13:12:11 +00:00
vendorcode vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_02 2020-11-19 18:26:58 +00:00
Kconfig soc/intel/xeon_sp: Move function debug macros 2020-10-29 16:44:19 +00:00