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Kyösti Mälkki 3af6aa10f7 arch/x86: Optimise PCI IO config accessor 
By design only 'reg' parameter can have the two least-
significant bits set. As 'reg' is often a constant,
'0xCFC + (reg & 3)' resolves to an immediate value
already at buildtime, unlike (addr & 3) which depends
of a constant (but non-immediate) value of 'dev' in
ramstage.

Change-Id: I6e729fe800c92b1ce4994ad2b4203072fa75a958
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31754
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14 11:36:09 +00:00
..
arm coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
arm64 coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
mips coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
ppc64 coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
riscv coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
x86 arch/x86: Optimise PCI IO config accessor 2019-03-14 11:36:09 +00:00