Raul E Rangel 3acc515bef soc/amd/{cezanne,common}: Enable IOMMU PCIe Device ... This change only enables the IOMMU device. We still require the IVRS table to take advantage of the IOMMU. This will happen when the picasso IVRS code is moved into common. BUG=b:190515051 TEST=lspci shows IOMMU device 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>		2021-07-12 12:30:33 +00:00
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amd	soc/amd/{cezanne,common}: Enable IOMMU PCIe Device	2021-07-12 12:30:33 +00:00
cavium	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
example	src: Introduce ARCH_ALL_STAGES_X86	2021-07-02 08:19:10 +00:00
intel	soc/intel/alderlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB	2021-07-12 04:37:07 +00:00
mediatek	soc/mediatek/mt8195: fine tune pmif spi hardware settings for stability	2021-07-12 02:54:36 +00:00
nvidia	cbfs: Replace more instances of cbfs_boot_locate() with newer APIs	2021-03-17 08:10:20 +00:00
qualcomm	sc7280: Add target specific GPIO pin definitions	2021-06-11 07:36:16 +00:00
rockchip	soc/rockchip/rk3399/sdram: Add channel to error message	2021-03-04 01:22:10 +00:00
samsung	commonlib/region: Turn addrspace_32bit into a more official API	2021-04-21 02:06:26 +00:00
sifive
ti	soc/ti/am335x/mmc.c: Fix memset length argument	2021-04-04 09:58:26 +00:00
ucb