coreboot/src/soc/intel
Andrey Petrov 3a94a3ba5b drivers/intel/fsp2_0: Split reset handling logic
FSP 2.0 spec only defines 2 reset request (COLD, WARM) exit codes. The
rest 6 codes are platform-specific and may vary. Modify helper function
so that only basic resets are handled and let SoC deal with the rest.

Change-Id: Ib2f446e0449301407b135933a2088bcffc3ac32a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15730
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-19 21:03:03 +02:00
..
apollolake drivers/intel/fsp2_0: Split reset handling logic 2016-07-19 21:03:03 +02:00
baytrail soc/intel/baytrail: use common Intel ACPI hardware definitions 2016-07-15 08:31:56 +02:00
braswell soc/intel/braswell: use common Intel ACPI hardware definitions 2016-07-15 08:32:09 +02:00
broadwell soc/intel/broadwell: use common Intel ACPI hardware definitions 2016-07-15 08:32:49 +02:00
common soc/intel/common: Add reset_prepare() for common reset 2016-07-19 20:20:13 +02:00
fsp_baytrail soc/intel/fsp_baytrail: use common Intel ACPI hardware definitions 2016-07-15 08:33:03 +02:00
fsp_broadwell_de soc/intel/fsp_broadwell_de: use common Intel ACPI hardware definitions 2016-07-15 08:32:35 +02:00
quark soc/intel/quark: use common Intel ACPI hardware definitions 2016-07-15 08:34:58 +02:00
sch intel/sch: Merge northbridge and southbridge in src/soc 2016-05-17 21:38:17 +02:00
skylake soc/intel/skylake: provide poweroff() implementation 2016-07-15 08:36:12 +02:00