Frans Hendriks 392d699570 src/soc/intel/braswell/romstage/romstage.c: Perform RTC init in romstage ... soc_rtc_init() is executed in ramstage The soc_rtc_init() needs to be executeed before FSP is called. Move the RTC init from ramstage to romstage. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ic19c768bf9d9aef7505fb9327e4eedf7212b0057 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/29397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2018-11-05 09:06:55 +00:00
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apollolake	src: Remove unneeded include <arch/ioapic.h>	2018-11-05 09:01:42 +00:00
baytrail	src: Add missing include <stdint.h>	2018-10-30 09:41:08 +00:00
braswell	src/soc/intel/braswell/romstage/romstage.c: Perform RTC init in romstage	2018-11-05 09:06:55 +00:00
broadwell	src: Add missing include <stdint.h>	2018-11-01 11:25:07 +00:00
cannonlake	soc/intel/cannonlake: Enable ISH from device	2018-11-05 09:06:49 +00:00
common	soc/intel: Enable GPIO functions in verstage	2018-11-02 16:06:53 +00:00
denverton_ns	src: Add missing include <stdint.h>	2018-11-01 11:25:07 +00:00
fsp_baytrail	src: Add missing include <stdint.h>	2018-10-30 09:41:08 +00:00
fsp_broadwell_de	src: Remove unneeded include <arch/ioapic.h>	2018-11-05 09:01:42 +00:00
icelake	src: Remove unneeded include <arch/ioapic.h>	2018-11-05 09:01:42 +00:00
quark	src: Add missing include <stdint.h>	2018-11-01 11:25:07 +00:00
skylake	src: Add missing include <stdint.h>	2018-11-01 11:25:07 +00:00
Kconfig	soc/intel/icelake: Do initial SoC commit	2018-10-26 11:20:54 +00:00