f8d4283e78
HPET General Capabilities and ID Register at offset 0x0 and Timer 0 Configuration and Capability Register at offset 0x100 are used to determine the generation of HPET ACPI tables. This patch adds macro definitions for these registers and fields. Definitions are from IA-PC HPET (High Precision Event Timers) Specification Revision 1.0a. Change-Id: I31413afcbfc42307e3ad3f99d75f33f87092d7aa Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84252 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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