coreboot/src
WANG Siyuan 385f0104e7 AMD Merlin Falcon: Add binary PI vendorcode files
Add all of the PI source that will remain part of coreboot to
build with a binary AGESA PI BLOB.  This includes the gcc makefiles,
some Kconfig, and the AGESA standard library functions.

Change vendorcode Makefile and Kconfig so that they can compile
AMD library files and use headers from outside the coreboot/src
tree.

Change-Id: Iad26689292eb123d735023dd29ef3d47396076ea
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10416
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-13 02:04:35 +02:00
..
acpi acpi/sata: add generic sata ssdt port generator 2015-06-07 01:24:47 +02:00
arch lenovo: Hide SMBIOS config 2015-06-11 13:20:56 +02:00
console consoles: remove unused infrastructure 2015-05-26 19:02:54 +02:00
cpu model_2065x: Use common i945-ivy TSEG SMM init. 2015-06-10 05:34:01 +02:00
device resource: Refactor IORESOURCE flags use 2015-06-10 05:51:51 +02:00
drivers lenovo: Hide SMBIOS config 2015-06-11 13:20:56 +02:00
ec lenovo: Move pc_keyboard_init to h8 init. 2015-05-29 07:45:55 +02:00
include Clearly define printk log level use cases. 2015-06-11 20:18:49 +02:00
lib stage_cache: use cbmem init hooks 2015-06-09 22:06:40 +02:00
mainboard google/jecht: fix MAC address programming when VPD not present 2015-06-12 10:55:07 +02:00
northbridge PCI subsystem: Drop PCI_64BIT_PREF_MEM option 2015-06-10 05:48:37 +02:00
soc pistachio: add DDR3 initialization code 2015-06-12 20:19:42 +02:00
southbridge AMD PI: remove unuseful ACPI code 2015-06-10 21:02:15 +02:00
superio superio/fintek: Add support for Fintek F81866AD-I 2015-06-12 22:41:52 +02:00
vendorcode AMD Merlin Falcon: Add binary PI vendorcode files 2015-06-13 02:04:35 +02:00
Kconfig lenovo: Hide SMBIOS config 2015-06-11 13:20:56 +02:00