coreboot/src
Furquan Shaikh 043976065b soc/intel/apollolake: Do not re-save BIST result
BIST result is already stored by arch/x86/bootblock_ctr0.S in
mm0. Also, eax does not contain BIST result by the time control
reaches bootblock_pre_c_entry. bootblock_crt0.S saves timestamp in mm2
which was being overwritten here. Thus, remove the saving of BIST
result from SoC code.

Change-Id: I65444689cf104c59c84574019f5daf82aab10bc7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14381
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-18 05:20:25 +02:00
..
acpi acpi/: add missing license header 2016-01-14 22:52:11 +01:00
arch bootblock_crt0: Use CR* macros from cpu/x86/cr.h 2016-04-15 01:31:16 +02:00
commonlib arch/x86: introduce postcar stage/phase 2016-03-23 14:24:30 +01:00
console arch/x86: introduce postcar stage/phase 2016-03-23 14:24:30 +01:00
cpu cpu/x86/tsc: Compile TSC timer for postcar as well 2016-04-11 17:56:57 +02:00
device payloads: add iPXE 'payload' build 2016-04-13 17:45:37 +02:00
drivers drivers/intel/fsp2_0: Add utility to recover MRC NV Storage data 2016-04-08 00:46:12 +02:00
ec ec/lenovo/h8: do not reset volume on s3 wakeup 2016-04-10 18:14:15 +02:00
include stddef.h: fix zeroptr's definition 2016-04-15 16:18:57 +02:00
lib program.ld: make sure that zeroptr isn't assigned to debug sections 2016-04-16 01:50:44 +02:00
mainboard mainboard/google/gru: Add license header to memlayout.ld 2016-04-16 03:13:00 +02:00
northbridge northbridge/amd/{lx,gx2}: remove immediate accesses of 0 2016-04-16 01:50:55 +02:00
soc soc/intel/apollolake: Do not re-save BIST result 2016-04-18 05:20:25 +02:00
southbridge southbridge/via: Update license headers 2016-04-13 17:36:14 +02:00
superio superio/smsc/mec1308: Fix AddressMax value for SMBX mailbox 2016-04-13 23:39:28 +02:00
vendorcode vendorcode/intel: Remove temporary Broadwell DE Kconfig symbol 2016-04-18 01:37:04 +02:00
Kconfig Kconfig: remove COMPRESS_PRERAM_STAGES option from x86 2016-03-11 16:52:38 +01:00