Martin Roth 37d1206c6e soc/amd/picasso: Get rid of VERSTAGE_SIZE ... Currently, the code and data in psp_verstage is ~59K. Adding the code to save vbnv to the SPI rom increases that to 66K. Getting rid of VERSTAGE_SIZE allows verstage to grow as it needs to. BUG=b:161366241 TEST=Build & Boot Morphius with VBOOT_VBNV_CMOS_BACKUP_TO_FLASH enabled Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ic6853b70073f9e781fc10402a2a47c9c8e0d49d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43486 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-07-16 22:20:27 +00:00
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amd	soc/amd/picasso: Get rid of VERSTAGE_SIZE	2020-07-16 22:20:27 +00:00
cavium	src: Remove unused 'include <types.h>'	2020-07-14 16:10:17 +00:00
intel	soc/intel/common/block/pmc: Select PMC on mainboard basis	2020-07-16 13:08:06 +00:00
mediatek	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
nvidia	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
qualcomm	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
rockchip	soc/rockchip/rk3399/display.c: Add missing include	2020-07-14 16:11:42 +00:00
samsung	soc/samsung/exynos5420: Drop dead code	2020-07-09 21:37:01 +00:00
sifive	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00