coreboot/src/soc/intel
Duncan Laurie 372b67e22b skylake: dptf: Add TSR3 thermal sensor and CPU code cleanup
- glados has more thermal sensors that could be used so add
another entry in the DTPF thermal sensor ACPI code.
- fix indentation block in cpu.asl.
- declare \_SB.MPDL as external (it is already CondRefOf)
so it does not need to be present in mainboard config if
the mainboard does not want to override the default.

BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: I1afe7013a24ee1215f5e968e25594f746bbdd17c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8d357437d06349039a94869b088c3c50b32933c0
Original-Change-Id: Ie87d52e735bf930a003e525cf1918789920922a5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297335
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11558
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09 20:19:12 +00:00
..
baytrail x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
braswell braswell: acpi: Allow DPTF thresholds to be defined at board-level 2015-09-09 20:18:23 +00:00
broadwell x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
common bootstate: remove need for #ifdef ENV_RAMSTAGE 2015-09-04 21:01:58 +00:00
fsp_baytrail intel/fsp_baytrail: Support Baytrail FSP Gold4 release 2015-07-21 22:32:23 +02:00
skylake skylake: dptf: Add TSR3 thermal sensor and CPU code cleanup 2015-09-09 20:19:12 +00:00