5bdac84c6b
Change-Id: Ie63499a4b432803a78af1c52d49e34cf1653ba17 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80589 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
157 lines
3.5 KiB
Text
157 lines
3.5 KiB
Text
## SPDX-License-Identifier: GPL-2.0-only
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config MISSING_BOARD_RESET
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bool
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help
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Selected by boards that don't provide a do_board_reset()
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implementation. This activates a stub that logs the missing
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board reset and halts execution.
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config ROMSTAGE_ADA
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bool
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help
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Selected by features that use Ada code in romstage.
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config RAMSTAGE_ADA
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bool
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help
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Selected by features that use Ada code in ramstage.
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config RAMSTAGE_LIBHWBASE
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bool
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select RAMSTAGE_ADA
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help
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Selected by features that require `libhwbase` in ramstage.
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config ROMSTAGE_LIBHWBASE
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bool
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select ROMSTAGE_ADA
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help
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Selected by features that require `libhwbase` in romstage.
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config FLATTENED_DEVICE_TREE
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bool
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help
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Selected by features that require to parse and manipulate a flattened
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devicetree in ramstage.
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config HAVE_SPD_IN_CBFS
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bool
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help
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If enabled, add support for adding spd.hex files in cbfs as spd.bin
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and locating it runtime to load SPD.
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config DIMM_MAX
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int
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default 4
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help
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Total number of memory DIMM slots available on motherboard.
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It is multiplication of number of channel to number of DIMMs per
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channel
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config DIMM_SPD_SIZE
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int
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default 256
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help
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Total SPD size that will be used for DIMM.
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Ex: DDR3 256, DDR4 512.
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config SPD_READ_BY_WORD
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bool
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config SPD_CACHE_IN_FMAP
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bool
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default n
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help
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Enables capability to cache DIMM SPDs in a dedicated FMAP region
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to speed loading of SPD data. Currently requires board-level
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romstage implementation to read/write/utilize cached SPD data.
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When the default FMAP is used, will create a region named RW_SPD_CACHE
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to store the cached SPD data.
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config SPD_CACHE_FMAP_NAME
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string
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depends on SPD_CACHE_IN_FMAP
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default "RW_SPD_CACHE"
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help
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Name of the FMAP region created in the default FMAP to cache SPD data.
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if RAMSTAGE_LIBHWBASE && !ROMSTAGE_LIBHWBASE
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config HWBASE_DYNAMIC_MMIO
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def_bool y
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endif
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if ROMSTAGE_LIBHWBASE
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config HWBASE_STATIC_MMIO
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def_bool y
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endif
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if RAMSTAGE_LIBHWBASE || ROMSTAGE_LIBHWBASE
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config HWBASE_DEFAULT_MMCONF
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hex
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default ECAM_MMCONF_BASE_ADDRESS
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config HWBASE_DIRECT_PCIDEV
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def_bool y
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endif
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config NO_FMAP_CACHE
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bool
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help
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If your platform really doesn't want to use an FMAP cache (e.g. due to
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space constraints), you can select this to disable warnings and save
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a bit more code.
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config ESPI_DEBUG
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bool
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help
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This option enables eSPI library helper functions for displaying debug
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information.
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config NO_CBFS_MCACHE
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bool
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help
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Disables the CBFS metadata cache. This means that your platform does
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not need to provide a CBFS_MCACHE section in memlayout and can save
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the associated CAR/SRAM size. In that case every single CBFS file
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lookup must re-read the same CBFS directory entries from flash to find
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the respective file.
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config CBFS_CACHE_ALIGN
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int
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default 8
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help
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Sets the alignment of the buffers returned by the cbfs_cache.
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config CBFS_PRELOAD
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bool
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depends on COOP_MULTITASKING
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help
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When enabled it will be possible to preload CBFS files into the
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cbfs_cache. This helps reduce boot time by loading the files
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in the background before they are actually required. This feature
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depends on the read-only boot_device having a DMA controller to
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perform the background transfer.
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config DECOMPRESS_OFAST
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bool
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depends on COMPILER_GCC
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default y
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help
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Compile the decompressing function in -Ofast instead of standard -Os
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config PROBE_RAM
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def_bool y if VENDOR_EMULATION
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help
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When enabled it will be possible to detect usable RAM using probe_ram
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function.
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config HAVE_CUSTOM_BMP_LOGO
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def_bool n
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depends on BMP_LOGO
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