coreboot/payloads/libpayload/drivers/usb
Furquan Shaikh 561bdd746c libpayload EHCI: Add memory barrier to EHCI driver
EHCI driver accesses mmio space using regular struct pointers. In order to avoid
any CPU re-ordering, memory barrier is required in async_set_schedule,
especially for arm64. Without the memory barrier, there seems to be re-ordering
taking place which leads to USB errors with some flash drives as well as
transfer errors in netboot.

BUG=chrome-os-partner:31533
BRANCH=None
TEST=With the memory barrier introduced, netboot for ryu completes transfer
without any error and finishes within 6-7 seconds.

Change-Id: Ic05d47422312a1cddbebe3180f4f159853604440
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/213917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
2014-08-26 03:06:01 +00:00
..
ehci.c libpayload EHCI: Add memory barrier to EHCI driver 2014-08-26 03:06:01 +00:00
ehci.h
ehci_private.h
ehci_rh.c
generic_hub.c
generic_hub.h
ohci.c
ohci.h
ohci_private.h
ohci_rh.c
quirks.c
TODO
uhci.c
uhci.h
uhci_private.h
uhci_rh.c
usb.c libpayload: usb: Try to avoid reusing device addresses 2014-04-30 10:00:43 +00:00
usb_dev.c
usbhid.c
usbhub.c
usbinit.c
usbmsc.c libpayload: usbmsc: Implement limited LUN support 2014-05-06 00:08:25 +00:00
xhci.c libpayload: usb: xhci: Fix TD size if it overflows 5 bits 2014-05-31 03:59:57 +00:00
xhci.h
xhci_commands.c
xhci_debug.c
xhci_devconf.c
xhci_events.c
xhci_private.h libpayload: usb: xhci: Fix TD size if it overflows 5 bits 2014-05-31 03:59:57 +00:00
xhci_rh.c