8dec5fcaf8
Adds a new flags field to the lb_spi_flash coreboot table to indicate if the SPI flash is operating in 4-byte address mode. This allows payloads to query the current address mode directly from the coreboot table, preventing redundant checks or re-enforcement of the mode. The flag is set based on the CONFIG_SPI_FLASH_FORCE_4_BYTE_ADDR_MODE configuration. Important: `erase_cmd` was reduced from uint32_t to uint8_t. Only the least significant byte was ever relevant, so this change ensures accurate type representation, maintains backward compatibility with existing coreboot table structures, and frees up space. BUG=b:417900125 TEST=Able to build google/bluey. Change-Id: I406536432b2a0c7f4108e5b33d5a20c272d917b0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> |
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| .. | ||
| acpi/thermal_zone | ||
| amd | ||
| ams | ||
| analogix/anx7625 | ||
| asmedia | ||
| aspeed | ||
| broadcom | ||
| camera | ||
| crb | ||
| efi | ||
| elog | ||
| emulation/qemu | ||
| generic | ||
| genesyslogic | ||
| gfx/generic | ||
| i2c | ||
| intel | ||
| ipmi | ||
| lenovo | ||
| maxim | ||
| mipi | ||
| mrc_cache | ||
| net | ||
| nxp/uwb | ||
| ocp | ||
| option | ||
| parade | ||
| pc80 | ||
| pcie | ||
| ricoh/rce822 | ||
| secunet/dmi | ||
| siemens/nc_fpga | ||
| sil/3114 | ||
| smbus | ||
| smmstore | ||
| sof | ||
| soundwire | ||
| spi | ||
| ti | ||
| tpm | ||
| uart | ||
| usb | ||
| vpd | ||
| wifi/generic | ||
| wwan/fm | ||