coreboot/src/soc/intel
Lijian Zhao 357e552562 soc/intel/common: Inject SMBIOS type 16 table
Add SMBIOS type 16 table for physical memory array, there's two item had
been left over.ECC and max capacity, as of now we set it to fixed value
as all the platform support by Intel common code don't support ECC
memory and so far the biggest capacity is 32GB.

BUG=b:129485635
TEST=Boot up with Sarien platform and check with dmidecode, the
following is the result:
Handle 0x000D, DMI type 16, 23 bytes
Physical Memory Array
        Location: System Board Or Motherboard
        Use: System Memory
        Error Correction Type: None
        Maximum Capacity: 32 GB
        Error Information Handle: Not Provided
        Number Of Devices: 2

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: If9c5831956ef273c84d831a2b1572b3442eed961
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32286
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-19 01:40:37 +00:00
..
apollolake soc/intel/cpulib: Remove redundent enable/disable functions 2019-04-13 03:25:46 +00:00
baytrail soc/intel/baytrail: Correct array bounds check 2019-04-08 14:13:39 +00:00
braswell {src,util}: Correct typo in comment and debug string 2019-04-08 14:10:20 +00:00
broadwell src: Use include <delay.h> when appropriate 2019-04-06 16:09:12 +00:00
cannonlake soc/intel/cnl: Generate DMAR ACPI table 2019-04-18 10:15:55 +00:00
common soc/intel/common: Inject SMBIOS type 16 table 2019-04-19 01:40:37 +00:00
denverton_ns {northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem() 2019-03-21 16:18:05 +00:00
fsp_baytrail src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI 2019-04-08 14:11:04 +00:00
fsp_broadwell_de src: Use include <delay.h> when appropriate 2019-04-06 16:09:12 +00:00
icelake soc/intel/cpulib: Remove redundent enable/disable functions 2019-04-13 03:25:46 +00:00
quark src: Use include <delay.h> when appropriate 2019-04-06 16:09:12 +00:00
skylake soc/skl: Update SkipExtGfxScan in UPD from devtree 2019-04-08 14:12:15 +00:00
Kconfig src/cpu: Remove dead sourced lines 2018-11-15 10:25:20 +00:00