coreboot/src/mainboard/emulation
Arthur Heymans bf037f3961 mb/emu/qemu-sbsa: Add GIC ITS and IORT for PCI MSI support
The QEMU sbsa-ref machine has a GICv3 ITS at 0x44081000 that handles
MSI/MSI-X translation for PCI devices. Without describing the ITS in
ACPI tables, Linux cannot set up MSI interrupts, causing warnings like:

  WARNING: CPU: 1 PID: 1 at drivers/pci/msi/msi.h:121 pci_msi_setup_msi_irqs+0x40/0x58
  xhci_hcd 0000:00:04.0: xHCI Host Controller

Add GIC ITS base address to the address map and implement
platform_get_gic_its() so the common MADT generation code emits
a GIC ITS entry.

Select ACPI_IORT and implement acpi_soc_fill_iort() to generate an
IORT table with an ITS Group node and a Root Complex node that maps
all PCI RIDs 1:1 to ITS device IDs.

Tested with Fedora 41 and a qemu-xhci USB controller.

Change-Id: I9366968aac855dae808f6f0c73f1d3ec644bbeff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91668
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2026-03-16 17:21:53 +00:00
..
qemu-aarch64
qemu-armv7
qemu-i440fx mb/emul/qemu-[q35,i440fx]: Create ICQR interrupt resource locally and use defined offset 2026-03-04 14:15:49 +00:00
qemu-power8
qemu-power9
qemu-q35 mb/emul/qemu-[q35,i440fx]: Create ICQR interrupt resource locally and use defined offset 2026-03-04 14:15:49 +00:00
qemu-riscv
qemu-sbsa mb/emu/qemu-sbsa: Add GIC ITS and IORT for PCI MSI support 2026-03-16 17:21:53 +00:00
spike-riscv
Kconfig
Kconfig.name