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Kyösti Mälkki 34cf5619f9 device/pci_ops: Reuse romstage PCI config for ramstage 
By changing the signatures we do not need to define
PCI config accessors separately for ramstage.

Change-Id: I9364cb34fe8127972c772516a0a0b1d281c5ed00
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-16 15:19:06 +00:00
..
acpi
arch device/pci_ops: Reuse romstage PCI config for ramstage 2019-03-16 15:19:06 +00:00
commonlib src: Drop unused '#include <halt.h>' 2019-03-16 11:46:58 +00:00
console coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
cpu src: Drop unused '#include <halt.h>' 2019-03-16 11:46:58 +00:00
device device/pci_ops: Reuse romstage PCI config for ramstage 2019-03-16 15:19:06 +00:00
drivers drivers/intel/fsp1_0: Deduplicate code 2019-03-16 09:01:50 +00:00
ec src: Drop unused '#include <halt.h>' 2019-03-16 11:46:58 +00:00
include device/pci_ops: Reuse romstage PCI config for ramstage 2019-03-16 15:19:06 +00:00
lib Remove leftover files 2019-03-14 11:32:06 +00:00
mainboard src: Drop unused '#include <halt.h>' 2019-03-16 11:46:58 +00:00
northbridge src: Drop unused '#include <halt.h>' 2019-03-16 11:46:58 +00:00
security vboot: rename symbols for better consistency 2019-03-15 12:59:29 +00:00
soc src: Drop unused '#include <halt.h>' 2019-03-16 11:46:58 +00:00
southbridge src: Drop unused '#include <halt.h>' 2019-03-16 11:46:58 +00:00
superio Remove leftover files 2019-03-14 11:32:06 +00:00
vendorcode vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake 2019-03-15 12:47:30 +00:00
Kconfig Kconfig: Add system type entries for common enclosures 2019-02-05 16:03:29 +00:00