coreboot/src/soc
Lijian Zhao 34745f613f soc/intel/common: Add whiskeylake celeron v-0 support
New whiskeylake v-0 stepping have changed the graphics device id from
0x3EA0 to 0x3EA1 for celeron, so declare that in common code. Also the
CPUID was changed from 806EB to 806EC, include that as well.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6
Reviewed-on: https://review.coreboot.org/c/31433
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-19 22:00:40 +00:00
..
amd soc/amd/common: Move PI refcode loader 2019-02-15 17:49:31 +00:00
cavium bootmem: add new memory type for BL31 2019-02-05 13:41:45 +00:00
imgtec (console,drivers/uart)/Kconfig: Fix dependencies 2018-11-21 22:49:48 +00:00
intel soc/intel/common: Add whiskeylake celeron v-0 support 2019-02-19 22:00:40 +00:00
mediatek bootmem: add new memory type for BL31 2019-02-05 13:41:45 +00:00
nvidia bootmem: add new memory type for BL31 2019-02-05 13:41:45 +00:00
qualcomm console: Change BOOTBLOCK_CONSOLE default to y 2019-01-14 12:13:55 +00:00
rockchip bootmem: add new memory type for BL31 2019-02-05 13:41:45 +00:00
samsung src: Don't use a #defines like Kconfig symbols 2019-01-28 13:41:28 +00:00
sifive riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV 2019-01-24 14:21:01 +00:00
ucb riscv: Add initial support for 32bit boards 2019-02-13 04:49:14 +00:00