David Hendricks 7d48ac5c7d soc/cavium: Integrate BDK files into coreboot ... * Make it compile. * Fix whitespace errors. * Fix printf formats. * Add missing headers includes * Guard headers with ifdefs Compile DRAM init code in romstage. Compile QLM, PCIe, RNG, PHY, GPIO, MDIO init code in ramstage. Change-Id: I0a93219a14bfb6ebe41103a825d5032b11e7f2c6 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/25089 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-07-03 15:53:32 +00:00
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amd	vc/amd/00670F00: Sync AGESA.h with PI blob	2018-06-13 21:20:32 +00:00
cavium	soc/cavium: Integrate BDK files into coreboot	2018-07-03 15:53:32 +00:00
google	security/tpm: Unify the coreboot TPM software stack	2018-06-04 20:33:07 +00:00
intel	vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.3	2018-05-22 15:52:11 +00:00
siemens	src: Fix all Siemens copyrights	2017-11-07 12:33:51 +00:00
Makefile.inc	soc/cavium: Integrate BDK files into coreboot	2018-07-03 15:53:32 +00:00