a6b3b4dd8f
Add common code design document support Intel SoCs such as Skylake, Cannonlake and Apollolake onwards. Documented items: *Introduction *Design Principle *Common code development and status *Common code structure *Benifits Change-Id: I5ade390cfb41c72f812d5cc4e00e67a5964721de Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> |
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| .. | ||
| _static | ||
| acpi | ||
| doxygen | ||
| getting_started | ||
| gfx | ||
| Intel | ||
| lessons | ||
| mainboard | ||
| northbridge | ||
| releases | ||
| RFC | ||
| soc | ||
| superio | ||
| technotes | ||
| thinkpad | ||
| vendorcode | ||
| abi-data-consumption.md | ||
| AMD-S3.txt | ||
| beginverbatim.tex | ||
| Binary_Extraction.md | ||
| cbfs.txt | ||
| codeflow.svg | ||
| conf.py | ||
| COPYING | ||
| coreboot_logo.png | ||
| corebootBuildingGuide.tex | ||
| Doxyfile.coreboot | ||
| Doxyfile.coreboot_simple | ||
| endverbatim.tex | ||
| gcov.txt | ||
| hypertransport.svg | ||
| index.md | ||
| Kconfig.tex | ||
| mainboard_io_trap_handler_sample.c | ||
| Makefile | ||
| Makefile.sphinx | ||
| POSTCODES | ||
| timestamp.md | ||
