Furquan Shaikh 340908aecf soc/intel/lpss: Provide common LPSS clock config ... Since there are multiple controllers in the LPSS and all use the same frequency, provide a single Kconfig option for LPSS_CLOCK_MHZ. BUG=b:35583330 Change-Id: I3c0cb62d56916e6e5f671fb5f40210f4cb33316f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19115 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)		2017-04-05 20:33:04 +02:00
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acpi	src/acpi: Capitalize ACPI and SATA	2016-07-31 19:25:40 +02:00
arch	arch/x86/acpigen: Allow writing buffers larger than 256 bytes	2017-04-03 04:53:03 +02:00
commonlib	commonlib: Wrap lines at 80 columns	2017-03-13 21:23:21 +01:00
console	console: Enable do_printk_va_list for VBOOT	2016-12-27 18:07:39 +01:00
cpu	AGESA: Disable CAR with empty stack	2017-04-05 15:02:43 +02:00
device	device/dram/ddr2: Add common ddr2 spd decoder	2017-03-10 11:17:27 +01:00
drivers	drivers/spi/tpm: Allow TPM_SPI to be used with PC80_SYSTEM.	2017-04-05 20:32:04 +02:00
ec	vboot: Move remaining features out of vendorcode/google/chromeos	2017-03-28 22:18:13 +02:00
include	drivers/spi/tpm: using tpm irq to sync tpm transaction	2017-04-05 20:29:36 +02:00
lib	src/lib/jpeg: Fix missing closing brace	2017-03-29 13:05:18 +02:00
mainboard	mainboard/google/reef: increase trackpad data hold time	2017-04-05 18:03:35 +02:00
northbridge	AGESA: Disable CAR with empty stack	2017-04-05 15:02:43 +02:00
soc	soc/intel/lpss: Provide common LPSS clock config	2017-04-05 20:33:04 +02:00
southbridge	cimx/sb800: Log southbridge call-sites	2017-04-03 06:17:18 +02:00
superio	superio/fintek: Add support for Fintek F71808A	2017-03-27 19:19:56 +02:00
vboot	Remove libverstage as separate library and source file class	2017-03-28 22:18:53 +02:00
vendorcode	vboot: Move remaining features out of vendorcode/google/chromeos	2017-03-28 22:18:13 +02:00
Kconfig	GDB_WAIT: Clarify Kconfig description	2017-03-14 22:20:47 +01:00