coreboot/src/soc/intel
Duncan Laurie bf713b04b6 soc/intel: Add support for USB ACPI code generation
To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for
any root hubs that may be present.

Recent Intel platforms route all ports to an XHCI controller
through a root hub.  This is supported by considering the root
hub to be USB port type 0, the USB 2.0 ports to be type 2, and
the USB 3.0 ports to be type 3.

This was tested with a Kaby Lake platform by adding entries to
the devicetree and checking the resulting SSDT.

Change-Id: I527a63bdc64f9243fe57487363ee6d5f60be84ca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-18 12:23:04 +00:00
..
apollolake soc/intel: Add support for USB ACPI code generation 2018-05-18 12:23:04 +00:00
baytrail {mb,nb,soc}: Remove references to pci_bus_default_ops() 2018-05-08 03:01:04 +00:00
braswell {mb,nb,soc}: Remove references to pci_bus_default_ops() 2018-05-08 03:01:04 +00:00
broadwell {mb,nb,soc}: Remove references to pci_bus_default_ops() 2018-05-08 03:01:04 +00:00
cannonlake {mb,nb,soc}: Remove references to pci_bus_default_ops() 2018-05-08 03:01:04 +00:00
common soc/intel: Add support for USB ACPI code generation 2018-05-18 12:23:04 +00:00
denverton_ns soc/intel/denverton_ns: Enable common code for CPU 2018-05-14 21:03:43 +00:00
fsp_baytrail {mb,nb,soc}: Remove references to pci_bus_default_ops() 2018-05-08 03:01:04 +00:00
fsp_broadwell_de soc/intel/fsp_broadwell_de: Spell verb *set up* with space 2018-05-08 14:23:48 +00:00
quark {mb,nb,soc}: Remove references to pci_bus_default_ops() 2018-05-08 03:01:04 +00:00
skylake soc/intel: Add support for USB ACPI code generation 2018-05-18 12:23:04 +00:00
Kconfig soc: Add Kconfig for each soc vendor 2017-10-23 17:18:32 +00:00