coreboot/src/commonlib
Bora Guvendik 3280b76729 storage/mmc: Fix wrong frequency setting for HS speed mode
Emmc spec, JEDEC Standard No. 84-B51, section 6.6.2.3, selection
flow of HS400 using Enhanced Strobe states that host should change
frequency to ≤ 52MHz when switching to HS speed mode first. In
current code, mmc_select_hs400() calls mmc_select_hs() to do this,
however caps are not cleared, so when switching from HS200 to HS400,
caps will still have DRVR_CAP_HS200, and mmc_recalculate_clock() will
set 200Mhz instead of ≤ 52MHz. As a result, switching to HS400 will
intermittently fail.

BUG=b:140124451
TEST=Switch speed from HS200 to HS400 on WHL RVP.

Change-Id: Ie639c7616105cca638417d7bc1db95b561afb7af
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37775
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19 17:48:15 +00:00
..
include/commonlib Drop ROMCC code and header guards 2019-12-19 03:25:05 +00:00
storage storage/mmc: Fix wrong frequency setting for HS speed mode 2019-12-19 17:48:15 +00:00
cbfs.c AUTHORS: Move src/commonlib copyrights into AUTHORS file 2019-09-10 12:50:35 +00:00
fsp_relocate.c AUTHORS: Move src/commonlib copyrights into AUTHORS file 2019-09-10 12:50:35 +00:00
iobuf.c AUTHORS: Move src/commonlib copyrights into AUTHORS file 2019-09-10 12:50:35 +00:00
lz4.c.inc cbfs: Add LZ4 in-place decompression support for pre-RAM stages 2016-02-22 21:38:37 +01:00
lz4_wrapper.c Move compiler.h to commonlib 2018-10-08 16:57:27 +00:00
Makefile.inc commonlib: Add Bubble sort algorithm 2019-02-26 11:14:41 +00:00
mem_pool.c AUTHORS: Move src/commonlib copyrights into AUTHORS file 2019-09-10 12:50:35 +00:00
region.c region: publicize region_end() and add region_device_end() 2019-11-11 10:28:09 +00:00
sort.c AUTHORS: Move src/commonlib copyrights into AUTHORS file 2019-09-10 12:50:35 +00:00