coreboot/src/cpu
Kyösti Mälkki 325b92f64a Intel cpus: cache actual size of the Flash ROM device
Cache was enabled for the last 4 MB below 4 GB when ramstage is
loaded. This does not cover the case of a 8 MB Flash and could
overlap with some system device placed at high memory.

Use the actual device size for the cache region. Mainboard
may override this with Kconfig CACHE_ROM_SIZE if necessary.

Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/641
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31 11:54:37 +02:00
..
amd Rename AMD_AGESA to CPU_AMD_AGESA 2012-03-16 22:40:35 +01:00
intel Intel cpus: cache actual size of the Flash ROM device 2012-03-31 11:54:37 +02:00
via Via Epia-N and C3: Set ioapic delivery type in Kconfig 2012-03-16 20:40:47 +01:00
x86 Make MTRR min hole alignment 64MB 2012-03-30 17:56:10 +02:00
Kconfig - Fix shortcoming in Kconfig when handling multiple "choice"s 2010-12-16 23:37:17 +00:00
Makefile.inc qemu: drop "northbridge.c" from src/cpu/... 2010-03-29 21:17:25 +00:00