Daisuke Nojiri 320647abda vboot2: add verstage ... Verstage will host vboot2 for firmware verification. It's a stage in the sense that it has its own set of toolchains, compiler flags, and includes. This allows us to easily add object files as needed. But it's directly linked to bootblock. This allows us to avoid code duplication for stage loading and jumping (e.g. cbfs driver) for the boards where bootblock has to run in a different architecture (e.g. Tegra124). To avoid name space conflict, verstage symbols are prefixed with verstage_. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac Original-Reviewed-on: https://chromium-review.googlesource.com/204376 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 27940f8916) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I42b2b3854a24ef6cda2316eb741ca379f41516e0 Reviewed-on: http://review.coreboot.org/8159 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)		2015-01-13 21:33:57 +01:00
..
intel	soc/intel/fsp_baytrail/gpio.c: Silence unused variable warning	2015-01-13 02:52:50 +01:00
nvidia	vboot2: add verstage	2015-01-13 21:33:57 +01:00
qualcomm	storm: Reserve memory from 0x4000_0000-0x414f_ffff	2015-01-09 06:21:08 +01:00
samsung	doxygen fixes: change @var to @param var	2015-01-06 06:33:25 +01:00
ucb	soc/riscv: Fix typo in src/soc/ucb/Makefile.inc.	2015-01-01 18:07:14 +01:00
Kconfig	Add UCB RISCV support for architecture, soc, and emulation mainboard..	2014-12-01 19:06:43 +01:00
Makefile.inc	Add UCB RISCV support for architecture, soc, and emulation mainboard..	2014-12-01 19:06:43 +01:00