coreboot/src/soc/intel
Lee Leahy 318ef96af3 soc/intel/quark: FSP MemoryInit Support
Add a dummy fill_power_state routine so that execution is able to reach
FSP MemoryInit.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
   *  Add "select DISPLAY_HOBS"
   *  Add "select DISPLAY_UPD_DATA"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
    CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if:
   *  MemoryInit returns 0 (success) and
   *  The the message "ERROR - Coreboot's requirements not met by FSP
binary!" is not displayed

Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13447
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10 02:42:21 +01:00
..
apollolake soc/intel: Add skeleton infrastructure for Apollolake SOC 2016-01-30 03:12:16 +01:00
baytrail ACPI: Fix IASL Warning about unused method for GBUF check 2015-12-10 16:30:50 +01:00
braswell drivers/intel/fsp1_1: Fix spelling error in API and copyright 2016-01-31 20:51:29 +01:00
broadwell chromeos: Remove CONFIG_VBNV_SIZE variable 2016-02-09 13:19:48 +01:00
common soc/intel/common: Use SoC specific routine to read/write MTRRs 2016-02-02 19:00:35 +01:00
fsp_baytrail src/: Chmod 644 all .c, .h, .asl, .inc, .cb, .hex, & Kconfig files 2016-01-29 16:57:11 +01:00
quark soc/intel/quark: FSP MemoryInit Support 2016-02-10 02:42:21 +01:00
skylake intel/skylake: Add gpio macro for unused GPIO pins 2016-02-09 19:44:57 +01:00