coreboot/src
Gabe Black 317850348e tegra124: Make the PLLX frequency selectable by model.
The PLLX provides the clock for the main cores which can run at different max
frequencies depending on the specific model of Tegra124. This change makes it
possible to select a model which will, in turn, select a frequency for PLLX.
The default is 2GHz which is the lowest maximum frequency.

BUG=chrome-os-partner:25467
TEST=Booted on nyan rev1. Verified that the selected PLLX frequency was 2GHz.
With a change that selects the right model for nyan, verified that the
corresponding frequency was selected.
BRANCH=None

Original-Change-Id: Iee3a615083dee97ad659ff41cbf867af2a0c325d
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/188602
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 1282015048)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I448a830f3184ad1afeadbd1c2974c7a27b03a923
Reviewed-on: http://review.coreboot.org/7409
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13 06:24:54 +01:00
..
arch arm: Redesign, clarify and clean up cache related code 2014-11-10 21:34:49 +01:00
console Copy u-boot sources as is and modify the tree to still build 2014-11-12 20:39:13 +01:00
cpu cpu/x86/smm/Makefile.inc: Fix up linkage rules 2014-11-11 12:34:27 +01:00
device device/dram/ddr3.c: Fix sizeof on array func param overflow 2014-11-08 07:09:34 +01:00
drivers drivers/intel/gma/intel_dp.c: Fix printf type-specifier 2014-11-11 14:42:18 +01:00
ec {arch,cpu,drivers,ec}: Don't hide pointers behind typedefs 2014-10-27 23:40:05 +01:00
include pci_ops.{c,h}: Don't hide pointers behind typedefs 2014-11-05 14:45:57 +01:00
lib src/lib/Makefile.inc: Allow rmodules to link under Clang 2014-11-12 18:13:57 +01:00
mainboard nyan: Update 924MHz BCT w/latest qual'd cfg, use 924 as default speed for 2GB 2014-11-13 06:24:42 +01:00
northbridge gm45: Don't crash if less than 4G of RAM are present. 2014-11-12 20:44:25 +01:00
soc tegra124: Make the PLLX frequency selectable by model. 2014-11-13 06:24:54 +01:00
southbridge sch: Move to implicit length patching 2014-11-09 12:55:13 +01:00
superio superio/ite: Use common dispatch for pnp entry/exit functions 2014-11-04 11:36:32 +01:00
vendorcode vendorcode/amd/agesa/f1{0,2,4,5}: Typo in header guard 2014-11-13 02:10:57 +01:00
Kconfig Kconfig: Hide DYNAMIC_CBMEM. 2014-11-09 02:03:24 +01:00