coreboot/src/soc
Kane Chen 314c4c3ed6 baytrail: use the setting in devicetree.cb to config USBPHY_COMPBG
USBPHY_COMPBG needs to be configured by project

BUG=chrome-os-partner:30690
BRANCH=none
TEST=emerge-rambi coreboot without problem
     checked the USBPHY_COMPBG is configured properly

Original-Change-Id: I05eee384d94cf5deeec14418bd78816df0b26a92
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208557
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 20a9c0ab7a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8bed3fa4e74e4bb4c93fa522d9df631bac2d9795
Reviewed-on: http://review.coreboot.org/8216
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-16 20:50:21 +01:00
..
intel baytrail: use the setting in devicetree.cb to config USBPHY_COMPBG 2015-01-16 20:50:21 +01:00
nvidia Revert "vboot2: add verstage" 2015-01-14 19:28:19 +01:00
qualcomm storm: Reserve memory from 0x4000_0000-0x414f_ffff 2015-01-09 06:21:08 +01:00
samsung doxygen fixes: change @var to @param var 2015-01-06 06:33:25 +01:00
ucb soc/riscv: Fix typo in src/soc/ucb/Makefile.inc. 2015-01-01 18:07:14 +01:00
Kconfig Add UCB RISCV support for architecture, soc, and emulation mainboard.. 2014-12-01 19:06:43 +01:00
Makefile.inc Add UCB RISCV support for architecture, soc, and emulation mainboard.. 2014-12-01 19:06:43 +01:00