3134a81525
When cbmem is initialized in romstage and postcar placed in the stage
cache + cbmem where it is run, the assumption is made that these are
all in UC memory such that calling INVD in postcar is OK.
For performance reasons (e.g. postcar decompression) it is desirable
to cache cbmem and the stage cache during romstage.
Another reason is that AGESA sets up MTRR during romstage to cache all
dram, which is currently worked around by using additional MTRR's to
make that UC.
TESTED on asus/p5ql-em, up/squared on both regular and S3 resume
bootpath. Sometimes there are minimal performance improvements
when cbmem is cached (few ms).
Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37196
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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| .. | ||
| bist.h | ||
| cache.h | ||
| cr.h | ||
| gdt.h | ||
| lapic.h | ||
| lapic_def.h | ||
| legacy_save_state.h | ||
| mp.h | ||
| msr.h | ||
| msr_access.h | ||
| mtrr.h | ||
| name.h | ||
| pae.h | ||
| post_code.h | ||
| save_state.h | ||
| smi_deprecated.h | ||
| smm.h | ||
| tsc.h | ||