coreboot/src
Duncan Laurie 3106d0ffce haswell: Misc updates from 1.6.1 ref code
These programming sequences were changed in the latest code.

Change-Id: Ia4b763a49542635713d11a9ee81f7e7f200bf841
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65612
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4466
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:50 +01:00
..
arch arm: Don't use const pointers with the write functions 2013-12-21 10:48:57 +01:00
console snprintf: lockless operation 2013-12-07 19:27:53 +01:00
cpu exynos5420: Fix some clock settings 2013-12-21 10:49:04 +01:00
device Add Kconfig options to override Subsystem Vendor and Device ID 2013-12-21 12:02:40 +01:00
drivers tpm: provide explicit tpm register access 2013-12-21 10:49:11 +01:00
ec chromeec: Add event methods for EC requested throttle 2013-12-21 12:02:14 +01:00
include Add a specific post code for S3 resume failures 2013-12-21 12:02:43 +01:00
lib Add simple hexdump function 2013-12-21 08:25:44 +01:00
mainboard slippy/falco/peppy: Fix EC wake events in S5 2013-12-21 12:02:46 +01:00
northbridge haswell: Misc updates from 1.6.1 ref code 2013-12-21 12:02:50 +01:00
southbridge haswell: Misc updates from 1.6.1 ref code 2013-12-21 12:02:50 +01:00
superio Correct file permissions. 2013-12-07 00:39:09 +01:00
vendorcode chromeos: Check for recovery reason code in shared data 2013-12-21 07:28:37 +01:00
Kconfig Add GRUB2 payload to build system 2013-11-19 01:07:25 +01:00