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coreboot/src/soc
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Martin Roth 30eda3edd7 fsp_baytrail: remove register option for TSEG size 
Set the UPD entry based on the Kconfig value instead of having two
separate places that the value needs to be set.

Change-Id: I3d32111b59152d0a8fc49e15320c7b5a140228a6
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7490
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2014-12-05 16:23:08 +01:00
..
intel fsp_baytrail: remove register option for TSEG size 2014-12-05 16:23:08 +01:00
nvidia Replace hlt with halt() 2014-12-02 10:25:55 +01:00
qualcomm ipq8064: Make timer code compile 2014-11-13 06:29:16 +01:00
samsung Replace hlt with halt() 2014-12-02 10:25:55 +01:00
ucb Add UCB RISCV support for architecture, soc, and emulation mainboard.. 2014-12-01 19:06:43 +01:00
Kconfig Add UCB RISCV support for architecture, soc, and emulation mainboard.. 2014-12-01 19:06:43 +01:00
Makefile.inc Add UCB RISCV support for architecture, soc, and emulation mainboard.. 2014-12-01 19:06:43 +01:00