coreboot/src
Martin Roth 30d88884c5 UPSTREAM: console/vtxprintf.c: cast precision to size_t for string length
If no maximum string length is specified, we're intentionally passing a
value of -1 to get the string length so that it's not limited.  This
makes checking tools unhappy, so actively cast it to size_t before
passing it into strlen to show that it's not an accident.

Addresses coverity issue 1129133 - Argument cannot be negative

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17479
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: I40f8f2101e170a5c96fcd39c217aa414f4316473
Reviewed-on: https://chromium-review.googlesource.com/415044
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-29 17:38:21 -08:00
..
acpi UPSTREAM: src/acpi: Capitalize ACPI and SATA 2016-08-04 23:37:57 -07:00
arch UPSTREAM: arch/x86: don't create new gdt in cbmem for relocatable ramstage 2016-11-29 03:22:17 -08:00
commonlib UPSTREAM: commonlib/include: remove NEED_VB20_INTERNALS 2016-11-21 11:53:31 -08:00
console UPSTREAM: console/vtxprintf.c: cast precision to size_t for string length 2016-11-29 17:38:21 -08:00
cpu UPSTREAM: intel sandy/ivy: Increase XIP cache with USE_NATIVE_RAMINIT 2016-11-21 11:53:52 -08:00
device UPSTREAM: device/dram/ddr3: Fix calculation CRC16 of SPD 2016-11-21 11:54:09 -08:00
drivers UPSTREAM: fsp2_0: implement stage cache for silicon init 2016-11-29 17:38:17 -08:00
ec google/chromeec: Add command to control USB PD role 2016-11-22 18:36:43 -08:00
include UPSTREAM: device/dram/ddr3: Calculate CRC16 of SPD unique identifier 2016-11-21 11:53:55 -08:00
lib UPSTREAM: intel post-car: Increase stacktop alignment 2016-11-21 11:53:20 -08:00
mainboard UPSTREAM: lenovo/x200/board_info.txt: Add SOIC-8 to ROM package 2016-11-29 17:38:02 -08:00
northbridge UPSTREAM: nb/intel: Fix some spelling mistakes in comments and strings 2016-11-29 17:38:19 -08:00
soc UPSTREAM: fsp2_0: implement stage cache for silicon init 2016-11-29 17:38:17 -08:00
southbridge UPSTREAM: intel/i82801gx: Reorder spaces in output 2016-11-29 17:38:05 -08:00
superio UPSTREAM: smscsuperio: map interrupt in smscsuperio_enable_serial() 2016-11-29 17:38:07 -08:00
vboot UPSTREAM: commonlib/include: remove NEED_VB20_INTERNALS 2016-11-21 11:53:31 -08:00
vendorcode UPSTREAM: google/chromeec: Add common infrastructure for boot-mode switches 2016-11-19 03:18:03 -08:00
Kconfig UPSTREAM: ACPI S3: Remove HIGH_MEMORY_SAVE where possible 2016-11-10 18:31:17 -08:00