coreboot/src
Lee Leahy 3071039fd7 UPSTREAM: arch/x86: Add bootblock and postcar support for SOC MTRR access
Quark does not support the rdmsr and wrmsr instructions.  Use SOC
specific routines to configure the MTRRs on Quark based platforms.
Add cpu_common.c as a build dependency to provide access to the routine
cpu_phys_address_size.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15846
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I43b7067c66c5c55b42097937e862078adf17fb19
Reviewed-on: https://chromium-review.googlesource.com/363936
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 22:56:06 -07:00
..
acpi UPSTREAM: arch/x86: provide common Intel ACPI hardware definitions 2016-07-15 08:39:52 -07:00
arch UPSTREAM: arch/x86: Add bootblock and postcar support for SOC MTRR access 2016-07-28 22:56:06 -07:00
commonlib UPSTREAM: cbmem: share additional time stamps IDs 2016-07-21 11:22:03 -07:00
console UPSTREAM: console/post: be explicit about conditional cmos_post_log() compiling 2016-05-26 03:21:57 -07:00
cpu UPSTREAM: cpu/x86: Support CPUs without rdmsr/wrmsr instructions 2016-07-28 22:56:04 -07:00
device UPSTREAM: device: include devicetree in bootblock stage 2016-07-28 22:55:59 -07:00
drivers UPSTREAM: cpu/x86: Support CPUs without rdmsr/wrmsr instructions 2016-07-28 22:56:04 -07:00
ec UPSTREAM: ec/google/chromeec: provide common SMI handler helpers 2016-07-15 16:50:24 -07:00
include UPSTREAM: cpu/x86: Support CPUs without rdmsr/wrmsr instructions 2016-07-28 22:56:04 -07:00
lib UPSTREAM: lib: Don't require ULZMA compression for postcar 2016-07-26 12:27:07 -07:00
mainboard UPSTREAM: soc/nvidia/tegra124: remove cache_policiy option 2016-07-28 22:55:57 -07:00
northbridge UPSTREAM: nb/intel/x4x: Fix CAS latency detection and max memory detection 2016-07-28 22:56:02 -07:00
soc UPSTREAM: cpu/x86: Support CPUs without rdmsr/wrmsr instructions 2016-07-28 22:56:04 -07:00
southbridge UPSTREAM: timestamp: Drop duplicate TS_END_ROMSTAGE entries 2016-07-21 11:22:15 -07:00
superio UPSTREAM: sio/winbond/w83667hg-a: Add pinmux defines for UART B 2016-05-31 12:07:04 -07:00
vendorcode UPSTREAM: google/chromeos: Add support for saving recovery reason across reboot 2016-07-25 15:02:24 -07:00
Kconfig UPSTREAM: src/lib: Enable display of cbmem during romstage and postcar 2016-07-26 12:27:02 -07:00