Michael Niewöhner 3054a19279 soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delay ... Correct the mask for the power cycle delay from 0xff to 0x1f, to represent the actual maximum value according to Intel graphics PRM for Haswell, Volume 2c and Intel graphics PRM for Broadwell, Volume 2c. Change-Id: Ib187f1ca6474325475e5ae4cc1b2ffbce12f10bf Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48957 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-12-29 20:19:52 +00:00
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amd	soc/amd/common/psp: Remove files from bootblock	2020-12-22 17:07:07 +00:00
cavium	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
example	x86: Add a minimal example SoC along with a board	2020-10-30 21:34:18 +00:00
intel	soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delay	2020-12-29 20:19:52 +00:00
mediatek	soc/mediatek/mt8192: Implement dramc base settings for each frequency	2020-12-29 14:35:45 +00:00
nvidia	Makefile: Add $(xcompile) to specify where to write xcompile	2020-12-23 03:40:35 +00:00
qualcomm	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
rockchip	drivers: Replace set_vbe_mode_info_valid	2020-12-17 06:21:56 +00:00
samsung	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
sifive	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
ti	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
ucb