coreboot/src/lib/generic_sdram.c
Lee Leahy 37f46e9b00 UPSTREAM: src/lib: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:

WARNING: line over 80 characters

TEST=Build and run on Galileo Gen2

Change-Id: Ic5caa0914f2ce7b1ff280735bf18b6f82ff39691
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7340217262
Original-Change-Id: I5fa3f8e950e2f0c60bd0e8f030342dc8c0469299
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18758
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454550
2017-03-14 07:25:27 -07:00

48 lines
1.1 KiB
C

#include <lib.h> /* Prototypes */
/* Setup SDRAM */
#if CONFIG_RAMINIT_SYSINFO
void sdram_initialize(int controllers, const struct mem_controller *ctrl,
void *sysinfo)
#else
void sdram_initialize(int controllers, const struct mem_controller *ctrl)
#endif
{
int i;
/* Set the registers we can set once to reasonable values */
for (i = 0; i < controllers; i++) {
printk(BIOS_DEBUG, "Ram1.%02x\n", i);
#if CONFIG_RAMINIT_SYSINFO
sdram_set_registers(ctrl + i, sysinfo);
#else
sdram_set_registers(ctrl + i);
#endif
}
/* Now setup those things we can auto detect */
for (i = 0; i < controllers; i++) {
printk(BIOS_DEBUG, "Ram2.%02x\n", i);
#if CONFIG_RAMINIT_SYSINFO
sdram_set_spd_registers(ctrl + i, sysinfo);
#else
sdram_set_spd_registers(ctrl + i);
#endif
}
/* Now that everything is setup enable the SDRAM.
* Some chipsets do the work for us while on others
* we need to it by hand.
*/
printk(BIOS_DEBUG, "Ram3\n");
#if CONFIG_RAMINIT_SYSINFO
sdram_enable(controllers, ctrl, sysinfo);
#else
sdram_enable(controllers, ctrl);
#endif
printk(BIOS_DEBUG, "Ram4\n");
}