Jonathan Neuschäfer 2f72a618f1 arch/riscv: Visually align trap frame information ... The pointers printed on unaligned memory accesses are now aligned to those printed at the end of print_trap_information. Change-Id: Ifec1cb639036ce61b81fe8d0a9b14c00d5b2781a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16983 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2016-10-15 00:28:14 +02:00
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arm	src/arch: Improve code formatting	2016-09-12 20:05:30 +02:00
arm64	arm64: Use 'payload' format for ATF instead of 'stage'	2016-10-06 21:49:52 +02:00
mips	build system: remove CBFSTOOL_PRE1_OPTS	2016-05-03 11:40:49 +02:00
power8	region: Add writeat and eraseat support	2016-06-24 20:48:12 +02:00
riscv	arch/riscv: Visually align trap frame information	2016-10-15 00:28:14 +02:00
x86	src/arch: Remove whitespace after sizeof	2016-10-07 18:08:48 +02:00