coreboot/src/cpu
Arthur Heymans 2f389f151a arch/arm: Pass cbmem_top to ramstage via calling argument
This solution is very generic and can in principle be implemented on
all arch/soc.

Instead trying to figure out which files can be removed from stages
and which cbmem_top implementations need with preprocessor, rename all
cbmem_top implementation to cbmem_top_romstage.

Mechanisms set in place to pass on information from rom- to ram-stage
will be placed in a followup commit.

Change-Id: If31f0f1de17ffc92c9397f32b26db25aff4b7cab
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-03 11:19:04 +00:00
..
amd lib/cbmem_top: Add a common cbmem_top implementation 2019-11-01 11:44:51 +00:00
armltd vboot2: add verstage 2015-01-27 01:41:40 +01:00
intel cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE 2019-11-03 06:15:35 +00:00
qemu-power8 AUTHORS: Move src/cpu copyrights into AUTHORS file 2019-09-10 12:51:22 +00:00
qemu-x86 cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE 2019-11-03 06:15:35 +00:00
ti arch/arm: Pass cbmem_top to ramstage via calling argument 2019-11-03 11:19:04 +00:00
via cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE 2019-11-03 06:15:35 +00:00
x86 cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE 2019-11-03 06:15:35 +00:00
Kconfig amdfam10-15: Rename DCACHE_BSP_STACK_SIZE 2019-08-18 08:09:21 +00:00
Makefile.inc Untangle CBFS microcode updates 2019-01-10 09:24:02 +00:00