Frans Hendriks 2e1fea408d superio: Add ASpeed AST2400 ... Add support for ASpeed AST2400. This device uses write twice 0xA5 to enter config mode. BUG = N/A TEST = ASRock D1521D4U Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>		2019-05-24 07:22:23 +00:00
..
acpi	arch/x86: Add common AMD ACPI hardware definitions	2017-11-10 19:15:38 +00:00
arch	src/mainboard/google: Adopt Mainboards to changed Type41 Func	2019-05-23 08:14:44 +00:00
commonlib	Renumber cbtable tag MMC_INFO	2019-05-23 10:43:30 +00:00
console	console: Move poor-man's atoi() into string.h	2019-05-23 08:43:12 +00:00
cpu	cpu/amd/quadcore: Remove variable set but not used	2019-05-23 08:53:35 +00:00
device	vboot: remove OPROM-related code	2019-05-15 17:50:08 +00:00
drivers	AGESA binaryPI: Sync STRUCT_NAME definitions	2019-05-23 09:00:19 +00:00
ec	ec/google/wilco: set diagnostic LEDs on boot failure	2019-05-22 20:01:25 +00:00
include	superio: Add ASpeed AST2400	2019-05-24 07:22:23 +00:00
lib	coreboot_tables: pass the early_mmc_wake_hw status to payload	2019-05-23 09:04:41 +00:00
mainboard	mb/google/hatch/variants: Fix DPTF sensor IDs	2019-05-23 09:02:48 +00:00
northbridge	nb/intel/pineview/early_init.c: Remove variable set but not used	2019-05-23 08:57:27 +00:00
security	post_code: add post code for failure to load next stage	2019-05-22 14:21:57 +00:00
soc	soc/intel/skylake: Add PCI Id for Kabylake DT	2019-05-23 11:58:01 +00:00
southbridge	sb/amd/cimx/sb800: Get rid of power button device in coreboot	2019-05-20 14:43:44 +00:00
superio	superio: Add ASpeed AST2400	2019-05-24 07:22:23 +00:00
vendorcode	AGESA binaryPI: Sync STRUCT_NAME definitions	2019-05-23 09:00:19 +00:00
Kconfig	src/Kconfig: Move DRAM section to src/lib/Kconfig	2019-05-20 10:58:56 +00:00