Felix Singer 2dff4f0688 mb/intel/kblrvp: Make use of chipset devicetree ... Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I1fd5f2a1c8adb5f379d7f3d0b54dca9c3ee6e2b3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>		2024-01-02 11:32:58 +00:00
..
acpi	x86: Separate CPU and SoC physical address size	2023-12-22 12:26:59 +00:00
arch	arch/x86/car.ld: Use VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE constant	2023-12-27 04:17:55 +00:00
commonlib	commonlib/bsd: Tag CBMEM IDs deprecated for crashlog	2023-12-20 04:29:25 +00:00
console
cpu	Revert "cpu/intel/common: Define build time physical address reserved bits"	2023-12-22 12:26:42 +00:00
device	x86: Separate CPU and SoC physical address size	2023-12-22 12:26:59 +00:00
drivers	drivers/intel/gma: Only show the choice when a VBT is to be added	2023-12-26 17:41:36 +00:00
ec
include	sb/intel/bd82x6x: Add defines for PCI IDs	2023-12-23 19:58:44 +00:00
lib
mainboard	mb/intel/kblrvp: Make use of chipset devicetree	2024-01-02 11:32:58 +00:00
northbridge	nb/intel/{gm45,sandybridge}: Use same indent levels for switch/case	2023-12-23 19:54:42 +00:00
sbom
security	security/tpm: Retrieve factory configuration for device w/ Google TPM	2023-12-31 03:18:42 +00:00
soc	soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verification	2024-01-02 03:40:18 +00:00
southbridge	sb/intel/bd82x6x/pch: Add method to identify PCH	2023-12-26 17:03:56 +00:00
superio
vendorcode	vendorcode/google/chromeos: Add API for Chromebook Plus check	2023-12-31 03:19:54 +00:00
Kconfig