huang lin 2d3d452d52 rk3288: configure l2ctlr in romstage ... Data RAM write latency: 2 cycles Data RAM read latency: 2 cycles Data RAM setup latency: 1 cycle Tag RAM write latency: 1 cycle Tag RAM read latency: 1 cycle Tag RAM setup latency: 1 cycle BUG=None TEST=Boot Veyron Pinky Change-Id: I1d710f65114be6a976aa3fe23b076e89c14ac8b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 421c2e5ba4 Original-Change-Id: Ic9c909b7913d434bd40016c6a820ddff7e991634 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223713 Original-Reviewed-by: Doug Anderson <dianders@chromium.org> Original-Commit-Queue: Doug Anderson <dianders@chromium.org> Reviewed-on: http://review.coreboot.org/9347 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>		2015-04-08 09:28:43 +02:00
..
arch	arm: Dump additional fault registers in abort handlers	2015-04-08 09:28:37 +02:00
console
cpu
device
drivers
ec
include	armv7: Add fine-grained page table support	2015-04-08 08:48:06 +02:00
lib	rmodule: remove cbmem_entry usage	2015-04-07 23:03:45 +02:00
mainboard	rk3288: configure l2ctlr in romstage	2015-04-08 09:28:43 +02:00
northbridge
soc	tegra132: Remove clamp_tristate_inputs() call	2015-04-08 09:28:40 +02:00
southbridge
superio
vendorcode	cbfs: Enforce media->map() result checking, improve error messages	2015-04-07 23:02:18 +02:00
Kconfig