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Emil Lundmark 2ad7ea07b8 mb/google/fizz: Add USB port info 
This adds all USB ports to the device tree. Additionally, it adds _PS0
and _PS3 ACPI methods for the visible USB A ports, which makes it
possible to control the port power (VBUS) of each port individually.

Change-Id: I80ba090f323fbf9fc2b333b1c647b7dfb3393ff6
Signed-off-by: Emil Lundmark <lndmrk@chromium.org>
Reviewed-on: https://review.coreboot.org/26472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-06-01 08:16:00 +00:00
..
acpi arch/x86: Add common AMD ACPI hardware definitions 2017-11-10 19:15:38 +00:00
arch arch/x86/include/arch: Remove space after __attribute__ 2018-05-31 15:28:00 +00:00
commonlib Introduce bootblock self-decompression 2018-05-22 02:44:14 +00:00
console Introduce bootblock self-decompression 2018-05-22 02:44:14 +00:00
cpu {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate 2018-05-31 15:10:21 +00:00
device device: Move find_dev_path() to device_const.c 2018-05-25 02:45:17 +00:00
drivers i210: Add additional PCI-ID to the i210 driver 2018-05-31 15:27:43 +00:00
ec chromeec platforms: Update ACPI throttle handler call 2018-05-29 22:35:07 +00:00
include cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiB 2018-05-31 15:09:30 +00:00
lib Remove AMD K8 cpu and northbridge support 2018-05-31 03:42:11 +00:00
mainboard mb/google/fizz: Add USB port info 2018-06-01 08:16:00 +00:00
northbridge {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate 2018-05-31 15:10:21 +00:00
security security/vboot: Remove redundent _verstage/_everstage/_verstage_size symbols 2018-05-14 16:24:28 +00:00
soc soc/amd/stoneyridge: Add ACPI device name lookup 2018-06-01 02:52:19 +00:00
southbridge Remove VIA vt8237r southbridge support 2018-05-31 03:47:24 +00:00
superio superio/ite/it8720f: Implement power control 2018-05-15 11:47:14 +00:00
vendorcode Remove leftover AMD CIMX RD890 vendorcode 2018-05-24 13:21:32 +00:00
Kconfig cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE 2018-05-31 15:08:48 +00:00