003d6397c6
The first steps to bring C7 and CX700 support back mainline. Most is skeleton copied from the `min86' example. The romstage entry is placed in the northbridge code, as that's where we'll perform raminit. Support to read the FSB frequency is added right away, same for a reset function (using CF9 reset), as both are required for a minimal build test. A mainboard VIA EPIA-EX is also introduced for build testing, and in later stages boot testing as well. Links: DS: https://theretroweb.com/chip/documentation/via-cx700-datasheet-feb06-666c8b172d347554179891.pdf PM: https://web.archive.org/web/20180616220857/http://linux.via.com.tw/support/beginDownload.action?eleid=141&fid=221 Change-Id: I66f678fae0d5a27bb09c0c6c702440900998e574 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82765 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
71 lines
3 KiB
Makefile
71 lines
3 KiB
Makefile
## SPDX-License-Identifier: GPL-2.0-only
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################################################################################
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## Subdirectories
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################################################################################
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subdirs-y += amd
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subdirs-y += armltd
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subdirs-y += intel
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subdirs-y += via
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subdirs-$(CONFIG_ARCH_X86) += x86
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subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86
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subdirs-$(CONFIG_CPU_POWER9) += power9
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$(eval $(call create_class_compiler,cpu_microcode,x86_32))
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################################################################################
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## Rules for building the microcode blob in CBFS
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################################################################################
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cbfs-files-$(CONFIG_USE_CPU_MICROCODE_CBFS_BINS) += cpu_microcode_blob.bin
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ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
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cbfs-files-y += cpu_microcode_blob.bin
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cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
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$(objgenerated)/microcode.bin: $(call strip_quotes,$(CONFIG_CPU_MICROCODE_HEADER_FILES))
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echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
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util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
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endif
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ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS),y)
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$(obj)/cpu_microcode_blob.bin: cpu_microcode_bins := $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES))
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endif
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# otherwise `cpu_microcode_bins` should be filled by platform makefiles
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# We just mash all microcode binaries together into one binary to rule them all.
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# This approach assumes that the microcode binaries are properly padded, and
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# their headers specify the correct size. This works fairly well on isolatied
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# updates, such as Intel and some AMD microcode, but won't work very well if the
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# updates are wrapped in a container, like AMD's microcode update container. If
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# there is only one microcode binary (i.e. one container), then we don't have
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# this issue, and this rule will continue to work.
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$(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) $(DOTCONFIG)
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for bin in $(cpu_microcode_bins); do \
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if [ ! -f "$$bin" ]; then \
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echo "Microcode error: $$bin does not exist"; \
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NO_MICROCODE_FILE=1; \
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fi; \
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done; \
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if [ -n "$$NO_MICROCODE_FILE" ]; then \
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if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS)" ]; then \
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echo "Try enabling binary-only repository in Kconfig 'General setup' menu."; \
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fi; \
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false; \
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fi
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$(if $(cpu_microcode_bins),,false) # fail if no file is given at all
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@printf " MICROCODE $(subst $(obj)/,,$(@))\n"
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@echo $(cpu_microcode_bins)
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cat $(cpu_microcode_bins) > $@
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cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
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cpu_microcode_blob.bin-type := microcode
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# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned.
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ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
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cpu_microcode_blob.bin-align := 64
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else
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cpu_microcode_blob.bin-align := 16
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endif
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ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
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cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
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endif
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